For set-associative mapping the cache control logic interprets
memory address (MAR)
·
A __________ register
specifies the address in memory for the next read or write.
memory buffer (MBR)
·
A _________ register
contains the data to be written into memory or receives the data read from
memory.
hardware failure
·
The most common
classes of interrupts are: program, timer, I/O and ________.
Timer
·
. A(n) _________
interrupt is generated by a timer within the processor and allows the operating
system to perform certain functions on a regular basis.
I/O
·
. A(n) ________
interrupt is generated by an I/O controller to signal normal completion of an
operation, request service from the processor, or to signal a variety of error
conditions
Disabled
·
A _________ interrupt
simply means that the processor can and will ignore that interrupt request
signal.
Interconnection
·
The collection of
paths connecting the various modules is called the _________ structure.
Bus
·
A __________ is a
communication pathway connecting two or more devices.
Control
·
The _________ lines
are used to control the access to and the use of the data and address lines
Dedicated
·
Bus lines can be
separated into two generic types: ________ and multiplexed
Asynchronous
·
With __________ timing
the occurrence of one event on a bus follows and depends on the occurrence of a
previous event.
Balanced
·
. With _________
transmission signals are transmitted as a current that travels down one
conductor and returns on the other.
Error
·
13. The QPI link layer
performs two key functions: flow control and _________ control.
PCI (peripheral
component interconnect)
·
14. The __________ is
a popular high-bandwidth, processor-independent bus that can function as a
mezzanine or peripheral bus.
flow control
·
15. The _________
function is needed to ensure that a sending QPI entity does not overwhelm a
receiving QPI entity by sending data faster than the receiver can process the
data and clear buffers for more incoming data.
External
·
__________ memory
consists of peripheral storage devices, such as disk and tape.
8
·
2. One byte equals
__________ bits.
Performance
·
3. From a user's point
of view the two most important characteristics of memory are capacity and
_____________.
Associative
·
5. _________ is a
random access type of memory that enables one to make a comparison of desired
bit locations within a word for a specified match, and to do this for all words
simultaneously, thus retrieving a word based on a portion of its contents
rather than its address.
memory cycle time
·
4. The three
performance parameters for memory are: access time, transfer rate, and
_________.
Transfer
·
The ________ rate is
the rate at which data can be transferred into or out of a memory unit.
magnetic surface
·
The most commonly used
physical types of memory are: semiconductor memory, __________ memory (used for
disk and tape), and optical and magneto-optical
Cost
·
The three key
characteristics of memory are capacity, access time, and _______.
Secondary
·
External, nonvolatile
memory is referred to as ___________ or auxiliary memory
Lines
·
The cache consists of
blocks called __________.
High-performance
·
. __________ computing
deals with super computers and their software.
execution units
·
The Pentium 4
processor core consists of four major components: fetch/decode unit, out-of-order
execution logic, memory subsystem, and __________.
ARM
·
An interesting feature
of the __________ architecture is the use of a small first-in-first-out (FIFO)
write buffer to enhance memory write performance.
Virtual
·
__________ memory is a
facility that allows programs to address memory from a logical point of view,
without regard to the amount of main memory physically available
Tag
·
For set-associative
mapping the cache control logic interprets a memory address as three fields:
Set, Word, and __________.
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